This invention relates generally to semiconductor devices. In particular, the present invention relates to a method and process for manufacturing a semiconductor structure or a semiconductor device.
The manufacturing of some semiconductor structures requires forming a silicon nitride layer on a semiconductor substrate and then patterning the silicon nitride layer. When using sub-micron photolithography to pattern a silicon nitride layer, an anti-reflective coating (ARC) is often used to minimize the effects of reflection from the silicon nitride layer.
One approach for patterning a silicon nitride layer requires the deposition of silicon nitride in a low-pressure chemical vapor deposition (LPCVD) chamber followed by the spin-coating of an organic ARC onto the semiconductor substrate. However, as device geometries shrink, organic ARC's may run into problems when trying to obtain optimum photolithography performance. Also, the spin-coating of an organic ARC tends to result in an uneven deposition of the organic ARC, which forms puddles in recessed regions in the underlying silicon nitride layer. As a result of the puddles, the thickness of the organic ARC in these regions is so high that the organic ARC cannot be completely etched off during later processing, thus leaving a residual amount of the organic ARC. The residual organic ARC acts as a mask and prevents the etching of portions of the underlying silicon nitride layer nitride. Stringers of unetched silicon nitride can result. These stringers increase the chances of device failure.
A second approach for patterning a silicon nitride layer requires the use of an inorganic ARC (IARC) made of silicon oxy-nitride or silicon-rich silicon nitride instead of an organic ARC. An IARC yields better photolithography performance and is free from the stringer problem, because the IARC is more evenly deposited on the semiconductor substrate. Currently, the IARC is commonly deposited using plasma-enhanced chemical vapor deposition (PECVD). However, IARC also has certain disadvantages: first, the deposition of the IARC requires an additional deposition step in a PECVD chamber; second, the placement of the IARC layer is limited to either the bottom or the top of the silicon nitride layer; and third, to prevent poisoning of a photoresist layer within the semiconductor device, the IARC layer needs to be capped by an oxide layer usually having a thickness of less than 100 Angstroms. Furthermore, because of the high deposition rate, the oxide layer is difficult to deposit in a controlled way in a PECVD chamber.